Investigation of Passivation Layers for Self-Aligned Top-Gate Amorphous InGaZnO Thin-Film Transistors with Metal-Reacted Low-Resistance Source/Drain

The metal reaction approach has been successfully utilized to fabricate high-performance self-aligned top-gate (SATG) oxide TFTs with low-resistance source/drain (S/D) regions. However, the stability remains a concern, as the metal-reacted S/D regions are susceptible to degradation during thermal processing. This work systematically investigated the passivation effects of PECVD SiO<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf>, Si<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</inf>N<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</inf>, and sputtered Al<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf>O<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</inf>. Results indicate that the 150 °C PECVD Si<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</inf>N<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</inf> passivation layer (PL) offers SATG TFTs superior stability under thermal, environmental and bias stress conditions, along with excellent scalability and well-maintained low S/D resistance, compared to other PLs.