Trends in 45nm Integrated Circuit Single-Event Upset Rates with Stacked-Transistor Layouts

Physics-based Monte Carlo predictions for single-event upset (SEU) rates in stacked-transistor designs are presented. Standard stacked-transistor designs are drawn either with transistor gates vertical (in-line) or horizontal (in-parallel). The zipper layout, a layout that has adjacent transistor gates periodically offset both horizontally and vertically, is compared to the standard layouts. Monte Carlo simulations predict comparable single-event upset (SEU) rates for the three aforementioned layout implementations of a data-flip-flop (DFF) in near-Earth orbital environments; these SEU rates are orders of magnitude lower than a non-stacked counterpart. The zipper layout is shown to be an effective area saving technique for stacked-transistor designs that does not compromise SEU performance.