Consideration of VFET for Ultimate Logic Scaling: A Design Perspective

In this work, the design of Vertical FET (VFET) for logic applications is comprehensively studied by the DTCO (Design Technology Co-Optimization) methodology. The nanosheet channel placement orientation and intrinsic device asymmetry are thoroughly investigated in the perspective of circuit design for the first time. For the nanosheet channel placement orientation, the Horizontal (along x-axis) Nanosheet has great layout flexibility, while the Vertical (along y-axis) Nanosheet design outperforms its counterpart by ~7% performance gain @ iso-power, with ~33% reduction of cell area. For the device asymmetry, significant Ieff improvement (~20%) and Cgd reduction (~30%) in the Forward mode were identified, leading to ~68% better performance @ iso-power in circuit simulation. A novel mixed design of Forward and Reverse mode is proposed for complex stdcell for the vertical nanosheets placement. This study brings new insights into the implementation of VFETs.