Heterogeneous 3D CFET with Hybrid Channel Configuration
Complementary field-effect transistors (CFETs) have been seriously studied for next-generation device architectures to improve PPA (power, performance, and area). However, many challenges remain, including process integration, structure optimization, implementation schemes (monolithic/sequential), etc. At the transistor level, unbalanced transport between n- and p-FET would be one of the most critical issues because CFETs inherently require the same width both for n- and p-FETs. Furthermore, new parameters such as spacing length between top and bottom FETs have emerged. Here, we discuss the opportunity for heterogeneous channel design to mitigate these issues.
Authors
- Youngkeun Park (ORCID: https://orcid.org/0009-0001-3307-0983)
- Byung Jin Cho (ORCID: https://orcid.org/0000-0003-3000-5403)
- Jin‐Gyun Kim (ORCID: https://orcid.org/0000-0002-2146-7609)
- Jaejoong Jeong (ORCID: https://orcid.org/0000-0003-1534-1329)
- Bongho Kim
- Dae‐Myeong Geum (ORCID: https://orcid.org/0000-0002-1965-5635)
- Sanghyeon Kim (ORCID: https://orcid.org/0000-0002-2517-4408)
- Jaeyong Jeong
- Younghyun Kim (ORCID: https://orcid.org/0000-0001-8072-1251)
- Seongkwang Kim (ORCID: https://orcid.org/0000-0002-9091-4054)
- Hyeong-Rak Lim
Institutions
- Korea Advanced Institute of Science and Technology (KR)
- Inha University (KR)
- Hanyang University (KR)
Publication Details
- Published
- 2025-03-09
- DOI
- https://doi.org/10.1109/edtm61175.2025.11041288
- Citations
- 1
- Primary Topic
- Semiconductor materials and devices
- Type
- article
- Field-Weighted Citation Impact
- 0.73
Funders
- Samsung