Cryogenic sEKV Compact Model Applied to 22 NM FDSOI Enabling Low-Temperature Circuit Simulation

This paper introduces the sEKV compact model for cryogenic circuit simulation, addressing the key challenge of cryoCMOS circuit validation. This model accurately represents the transistor and circuit DC characteristics at both room and cryogenic temperatures of a commercial 22 nm FDSOI technology using only a few parameters. It serves as a practical alternative solving the lack of PDKs currently available for the design of cryo-CMOS circuits. To reach a wider audience, the Verilog-A code of the model is available as open source.