Direct Backside Contact Impact on 3-Dimensional Stacked FET SRAM Beyond 1nm Node

Direct Backside Contact (DBC) is crucial for reducing the logic standard cell and SRAM bitcell area in 3Dimensional Stacked FET (3DSFET) beyond 1nm node. Among various Back Side Interconnection (BSI) methods, we propose using DBC for the PMOS device and front-side interconnection for the NMOS device. This approach achieves a 28 % improvement in SRAM bitcell area scalability, a reduction in external resistance, and an increase in PD and PG transistor on-current by 7.2 %, IREAD by 4.7 %, and Gamma by 7.2 %, demonstrating DBC's effectiveness for advanced CMOS scaling in 3DSFET architecture.