Understanding the Impact of Discrete Trap Positions and Mapping the Hysteresis Dynamics in $\text{MoS}_{2}$ FETs by Advanced TCAD Modeling

Locally increased defect densities in gate insulators, for instance due to not properly adjusted processing, could present a serious reliability problem for 2D FETs. By doing advanced TCAD modeling, here we for the first time demonstrate that hysteresis dynamics in <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\text{MoS}_{2}$</tex> FETs may depend on the trap position in oxide. Furthermore, we show that in some positions defects may cause a localized hysteresis of both signs and introduce the universal hysteresis mapping method to properly benchmark this behavior. Finally, we revisit previous experimental results for <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\text{FAB} \text{MoS}_{2}$</tex> FETs and show that our TCAD-inspired method can add more understanding to the observed hysteresis dynamics.