Impact of Load-Si Thickness and Punch-Through Stopper Doping on the Electrical Performance of SOI Gate-All-Around Field-Effect Transistors
In this article, we systematically investigate the effects of load-Si thickness and punch-through stopper (PTS) on the electrical characteristics of SOI GAAFET through 3D technology computer-aided design (TCAD). When Npts increases to <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$5 \times 10^{18} \text{cm}^{-3}$</tex>, the leakage of SOI GAAFET with a thick load-Si has significantly suppressed. When <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathrm{T}_{\text{Si }}$</tex> is 5 nm or below, it is not necessary to apply the PTS scheme to achieve excellent electrical properties, thanks to stronger gate control and quantum effects.
Authors
- Haoyan Liu (ORCID: https://orcid.org/0000-0002-6305-2065)
- Yan Li (ORCID: https://orcid.org/0000-0002-4425-0488)
- Jiayi Zhang (ORCID: https://orcid.org/0000-0002-0601-5794)
- Yongliang Li (ORCID: https://orcid.org/0000-0002-5590-861X)
- Longyu Sun (ORCID: https://orcid.org/0009-0007-3687-7997)
- Xi Zhang (ORCID: https://orcid.org/0009-0007-1790-5884)
Institutions
- Chinese Academy of Sciences (CN)
- Institute of Microelectronics (CN)
- Beijing Information Science & Technology University (CN)
Publication Details
- Published
- 2025-03-09
- DOI
- https://doi.org/10.1109/edtm61175.2025.11040734
- Primary Topic
- Advancements in Semiconductor Devices and Circuit Design
- Type
- article
- Field-Weighted Citation Impact
- 0.00