Global Stress Analysis in Fin Patterned Si/SiGe Multilayer Nanosheets for Nanosheet-Based CMOS Device Technology

Si/SiGe nanosheet-based CMOS technology is essential for 3nm semiconductor nodes and below. This study investigates stress in Si/SiGe superlattice nanosheets after fin patterning on silicon substrates. SiGe nanosheets (Ge mole fraction 0.35) exhibit 2.17 GPa compressive stress, while Si nanosheets are initially stress-free. After patterning, tensile stress induced in Si nanosheets stress due to relaxation in SiGe. These findings provide insights into stress engineering, crucial for improving performance and reliability of nanosheet-based CMOS and heterostructure devices.