Enabling Broader Memory Windows by Double-Gate Nanosheet Ferroelectric FETS for Next-Generation Non-Volatile Memory Storage

In this work, we present a novel lateral electric field-driven transistor that leverages an asymmetric double-gate nanosheet (DGNS) design to optimize the balance between ferroelectric (FE) layer scaling and memory window (MW) expansion. This device architecture, implemented through precise digital etching, defines a controllable active area together with a self-aligned etching method to facilitate the formation of the NS channels, significantly improving fabrication efficiency. The unique design separates read and write functions, by taking advantages of body effect and a high surface-to-volume ratio of channel to expand the MW without compromising electrostatic integrity. These innovations provide enhanced performance and scalability, positioning the proposed device as a viable candidate for advanced applications in next-generation electronic systems and memory storage technologies.