A 12-Bit Fully Differential SAR/SS ADC Architecture Based on Scale Reference for High-Speed CMOS Image Sensors
This paper presents a 12-bit fully differential SAR/SS ADC designed for high-speed CMOS image sensors, that uses SAR ADC with a scaled reference CDAC for coarse quantization and SS ADC with a current-steering ramp generator for fine quantization. The circuit, designed in a 110 nm 1P4M CMOS process, saves at least 80% of chip area and achieves a favorable speed-area trade-off. Simulation results indicate a conversion time of 3.9μs at a clock frequency of 20MHz.
Authors
- Peng Feng (ORCID: https://orcid.org/0000-0002-7420-2161)
- Weizhe Zhang (ORCID: https://orcid.org/0000-0003-4783-876X)
- Nanbo Chen
- J. Liu (ORCID: https://orcid.org/0000-0002-8397-7620)
- Bailin Zhang (ORCID: https://orcid.org/0000-0003-2759-7727)
- Liyuan Liu (ORCID: https://orcid.org/0009-0005-5898-8466)
- Gang Wang (ORCID: https://orcid.org/0000-0001-9110-3942)
- Ziyang Hu (ORCID: https://orcid.org/0000-0001-7996-2963)
- Jingyang Chen
- Changhui Yang
- Nanjian Wu (ORCID: https://orcid.org/0000-0001-8022-0262)
Institutions
- Ningbo University (CN)
- Chinese Academy of Sciences (CN)
- Institute of Semiconductors (CN)
Publication Details
- Published
- 2025-03-09
- DOI
- https://doi.org/10.1109/edtm61175.2025.11040553
- Primary Topic
- CCD and CMOS Imaging Sensors
- Type
- article
- Field-Weighted Citation Impact
- 0.00
Funders
- National Natural Science Foundation of China
- National Key Research and Development Program of China