Self-Heating and Process Induced Performance Barrier on Complementary Field Effect Transistor: A Reliability Perspective

The vertical nanosheet (channels) stacking and aligned in such a way that <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\text{nFET}$</tex> is kept over <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\text{pFET}$</tex>, or vice-versa, raises severe reliability concerns in Complementary FET (CFET). In this paper, using well-calibrated TCAD models, all the related reliability issues are being analyzed, such as: (i) the role of dielectric separation wall <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(\mathrm{D}_{\mathrm{S}\mathrm{W}})$</tex> in electrical and thermal cross-talk from <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\text{nFET}$</tex> to <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\text{pFET}$</tex> and vice-versa; (ii) the impact of self-heating effect (SHE) on self- and the other side of the <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathrm{D}_{\mathrm{S}\mathrm{W}};(iii)$</tex> impact of random dopant fluctuations (RDF) on threshold voltage <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(\mathrm{V}_{\mathrm{t}\mathrm{h}});(iv)$</tex> impact of line-edge roughness (LER) on <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathrm{I}_{\mathrm{O}\mathrm{N}}$</tex> and <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathrm{V}_{\mathrm{t}\mathrm{h}};(v)$</tex> effect of metal grain granularities (MGG) and the ratio of grain size to gate area (RGG) on device merits, viz <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathrm{I}_{\mathrm{O}\mathrm{N}}$</tex> and <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathrm{V}_{\mathrm{t}\mathrm{h}}$</tex>; and finally (vi) the device aging is predicated using the 'shift in <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathrm{V}_{\mathrm{t}\mathrm{h}}$</tex> ‘ by <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\pm 50\text{mV}$</tex> Thus, the proposed analysis benchmarks a reliable CFET design.