Optimization of RRAM Read Performance and Area Efficiency: A Large-Scale and Low-Parasitic Array with Novel Interconnection Schemes

This study presents an optimization design for RRAM arrays, highlighting the trade-offs in power consumption, read speed, area efficiency, and array scalability of 1T1R arrays. To address these limitations, we propose a novel large-scale and low-parasitic array design with shared SLs across multiple rows. This design effectively reduces read power and latency while enhancing array scalability and area efficiency. Implemented in a 28nm process, it achieves an 8.6% improvement in area efficiency and a 76% enhancement in array scale compared to the conventional design, while maintaining advantages in read speed and power consumption.