Characterization of a 1T-Floating Body DRAM Cell in Bulk Silicon MOSFETS for Cryogenic Memory Applications

In this work, we characterized the SMIC 180 nm bulk silicon MOSFETs down to 6 K and experimentally validated their application in cryogenic capacitor-less floating body dynamic random-access memory (DRAM). At 6 K with a drain voltage of 1.8 V, the device demonstrates a hysteresis loop with a width exceeding 0.2 V, a high-to-low drain current ratio of 10<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">9</sup>. Additionally, it exhibits a sense margin that exceeds <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$650 \mu ~\mathrm{A}$</tex>, a long retention time (<tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$&gt;10^{3} ~\mathrm{s}$</tex>), and a high-speed memory operation (50 ns). These characteristics make it a promising candidate for a compact, capacitor-less, single-transistor memory.