Monolithic 3D Integration of 2D Devices

Monolithic three-dimensional (3D) integration of 2D materials represents a major breakthrough in semiconductor technology, offering higher device density and multifunctionality [1]. Recently, we achieved large-scale, wafer-level 3D integration of MoS<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> and WSe<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> field-effect transistors (FETs) across multiple tiers [2]. This work includes 2-tier integration of MoS<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> FETs with over 10,000 devices per tier and 3-tier integration of both n-type MoS<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> and p-type WSe2 FETs, with approximately 500 devices per tier (Fig. 1). The 3-tier architecture combines multifunctional capabilities, such as logic, memory storage, and sensing, into a single chip. Aggressively scaled MoS<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> FETs with channel lengths as short as 45 nm further demonstrate the scalability of this approach. The entire integration process is BEOL-compatible, using low-temperature techniques to prevent degradation of lower-tier devices, marking a significant step toward highly dense, multifunctional 3D integrated circuits based on 2D materials.