An Rram-Based Multi-Mode and Pipelined Pooling Scheme in Computing-In-Memory for Convolutional Neural Networks

RRAM-based computing-in-memory acceleration for convolutional neural networks (CNNs) has shown promising advancements across various fields. In this work, to further accelerate the pooling operations between convolution layers, we propose an RRAM-based pooling scheme for CIM that enables in-suit pooling without extra data transfer and supports flexible switching between multi-mode (max, sum, and mean) pooling functions. We achieve pipelined operation by integrating RRAM arrays and ADCs within the CIM system. Validation using the VGG-11 architecture demonstrates a significant reduction of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$10.4 \times$</tex> in latency and <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$9.9 \times$</tex> in energy consumption with negligible accuracy loss (0.04%@6 bit).

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Published
2025-03-09
DOI
https://doi.org/10.1109/edtm61175.2025.11041096
Primary Topic
Advanced Memory and Neural Computing
Type
article
Field-Weighted Citation Impact
0.00

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article

An Rram-Based Multi-Mode and Pipelined Pooling Scheme in Computing-In-Memory for Convolutional Neural Networks

Ru Huang, Yi Qin Gao, Yimao Cai, Zongwei Wang et al.
Advanced Memory and Neural Computing
article

An Rram-Based Multi-Mode and Pipelined Pooling Scheme in Computing-In-Memory for Convolutional Neural Networks

Ru Huang, Yi Qin Gao, Yimao Cai, Zongwei Wang, Lin Bao
article en

Abstract

RRAM-based computing-in-memory acceleration for convolutional neural networks (CNNs) has shown promising advancements across various fields. In this work, to further accelerate the pooling operations between convolution layers, we propose an RRAM-based pooling scheme for CIM that enables in-suit pooling without extra data transfer and supports flexible switching between multi-mode (max, sum, and mean) pooling functions. We achieve pipelined operation by integrating RRAM arrays and ADCs within the CIM system. Validation using the VGG-11 architecture demonstrates a significant reduction of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$10.4 \times$</tex> in latency and <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$9.9 \times$</tex> in energy consumption with negligible accuracy loss (0.04%@6 bit).

Peking University (CN)
National Natural Science Foundation of China, Beijing Nova Program
Openalex Percentile: Top 87%
Advanced Memory and Neural Computing
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