Impact of Gate Misalignment on Analog Performance Metrics of Nanoscale Independent Dual-Gate IGZO FETs for BEOL-Memory Sense Amplifier Design

For high-density 3D DRAM, the voltage drops of Through-Silicon-Via are nonnegligible among stacks of layers, requiring high-gain sense amplifier (SA) design. Considering back-end of line (BEOL) compatibility, independent dual-gate (IDG) IGZO FETs are promising not only for multi-bit DRAM design but also for applications in SA input transistors. This paper investigates the important analog figures of merit (FOMs) of DG IGZO FETs under various operating conditions. TCAD simulations validated by experimental data reveal that top-gate misalignment (ranging from 25% to 100%) exhibits electric field distribution variations. The trade-off between transconductance generation factor and intrinsic gain is obviously observed. Such a top-gate misalignment effect causes threshold voltage shifts and circuit mismatches in DRAM SAs, and the mismatch can be compensated by independent top-gate biasing, enabling threshold voltage modulation. IDG IGZO FETs indicate superior gain performance compared to single-gate IGZO FETs and lower leakage current than Si-based FETs, which are critical for SA input transistors. These findings provide important guidance for optimizing dual-gate IGZO FETs in analog applications, particularly for BEOL-memory SAs that need both high gain and fast response speed.