Novel ergodic sequential logic neural oscillator: Bifurcation theory based systematic design procedure and efficient FPGA implementation

This study presents a novel ergodic sequential logic (ESL) neural oscillator and proposes its novel theoretical analysis procedures based on essential concepts in the bifurcation theory, such as the concepts of center manifold, Poincare map, and fixed point. Based on these analysis procedures, a novel design procedure for the oscillator is also proposed. Using the proposed design procedure, the oscillator is implemented on a field programmable gate array. The oscillator is shown to be capable of realizing desired characteristics through experimentation. Comparisons indicate that the presented oscillator is much more hardware-efficient than a commonly used digital-processor-based neural oscillator. It is also discussed that the presented neural oscillator will be useful for developing many kinds of hardware-efficient neuromorphic application systems.