Variable-parallelism reconfigurable architecture for efficient and flexible CNN acceleration
DNN accelerators, which can efficiently perform computations on multiple models, are recently in demand. In this study, we proposed an architecture that efficiently performs computations by switching the computation method according to the model to be computed, achieving switching in parallelism with no data movement between the memories. Compared to other architectures, this architecture improved the PE utilization by up to 14% on existing models. In addition, as parallelism can be switched, higher PE utilization was achieved with various types of DNN layers, where the PEs are expected to serve as generic architectural primitives, even for future DNN model structures.
Authors
- Takao Marukame (ORCID: https://orcid.org/0000-0001-5954-828X)
- Kota Ando (ORCID: https://orcid.org/0000-0001-8648-3768)
- F. Arai (ORCID: https://orcid.org/0009-0009-5890-7303)
- Tetsuya Asai (ORCID: https://orcid.org/0000-0003-1158-9810)
- Yoshiro Inoue
- Atsushi Hori (ORCID: https://orcid.org/0009-0000-1961-7404)
Institutions
- Hokkaido University (JP)
Publication Details
- Journal
- Nonlinear Theory and Its Applications IEICE
- Published
- 2025-01-01
- DOI
- https://doi.org/10.1587/nolta.16.422
- Primary Topic
- CCD and CMOS Imaging Sensors
- Type
- article
- Field-Weighted Citation Impact
- 0.00
Funders
- Japan Society for the Promotion of Science