Robust Impact Ionization Driven PDSOI FinFET Capacitorless 1T-DRAM with Low-k Spacer for Advanced Memory Applications

A gate-source/drain underlap partially depleted-silicon on insulator FinFET (PDSOI)-based capacitorless 1T-DRAM with a spacer is proposed, focusing on key performance parameters for DRAM applications, including high sense margin, retention time, low density, low power consumption, and high-speed operation. The proposed device exhibits an excellent sense margin indicating good read-out performance across temperatures. Additionally, it achieves a good retention time, demonstrating strong data retention capability. The design improves memory density and scalability by removing the need for complex capacitors and leveraging 3D FinFET structures for charge storage. Sensitivity analysis of body biasing shows a negligible effect on the sense margin, though retention time experiences slight variations due to changes in leakage current. Additionally, the robustness of the device is thoroughly evaluated through simulations that involve different isolation dielectrics and spacer materials. These simulations assess the impact of various dielectric properties and spacer configurations on the device performance, stability, and reliability under varying operating conditions. The complete performance of the device is simulated using the ATLAS TCAD tool validating its potential for delivering high performance, low power consumption, and cost-effective solutions for DRAM applications.