Failure boundaries of chip solder joints under impact conditions

In addressing the issue of damage and failure of chip solder joints under severe overload impact conditions, this study meticulously analyzes the distinct response characteristics of the structure across low, medium, and high frequency bands under impact loading. Building upon this analysis, a damage and failure boundary for chip solder joints is established on the pseudo-velocity shock response spectrum in a four-logarithmic coordinate system. Focusing on a typical chip boardlevel circuit as the research subject, a numerical simulation study on the impact damage boundary of chip solder joints is conducted. The findings reveal a high degree of agreement between the damage and failure boundaries determined through finite element analysis and those calculated from the shock response spectrum. The methodology proposed in this paper for constructing the failure damage boundary of chip solder joints effectively determines the failure conditions of solder joints, thereby providing a theoretical foundation for the reliability design and failure analysis of integrated circuits in environments subjected to intense mechanical shock.