Optimization Study for Enhancing Internal Module Communication Efficiency in Integrated Circuits

In backend VLSI design, congestion and timing are critical factors. However, due to the high complexity of semiconductor design and the specialization required at each design stage, frontend and backend designs are often conducted independently. This can lead to difficulties in achieving overall optimization of the design. This paper addresses this issue not by solving it comprehensively but by focusing specifically on the communication methods between internal modules of the chip. We analyze cell placement and routing congestion and explore methods to optimize communication efficiency by considering timing issues in advance. Specifically, the study compares and analyzes the efficiency of different methods for selecting target modules by the primary module under various conditions. Focusing on the commonly used Chip Select (CS) and Identification (ID) methods, we examine how each method’s complexity and performance are affected by the number and type of target modules controlled and propose design approaches to optimize module-to-module communication. This paper offers recommendations on module selection methods based on design conditions and provides practical guidelines for designers to enhance communication efficiency effectively.