Adaptive Equalization for 32 Gbps SerDes Receivers Using a Floating Decision Feedback Equalizer Algorithm

With the rapid advancement of cloud computing, 5G networks, and the Internet of Things, the demand for high-speed data transmission has surged. Serializer and deserializer (SerDes) technology represents a critical solution for high-speed data transmission, with the adaptive equalization algorithm at the receiver playing a vital role in enhancing SerDes performance. The SerDes employs Non-Return-to-Zero (NRZ) encoding and features a receiver that includes a Variable Gain Amplifier (VGA), a Continuous Time Linear Equalizer (CTLE), and a Decision Feedback Equalizer (DFE) with 8 fixed taps and 4 floating taps. CTLE and VGA utilize a negative capacitance structure to enhance gain, while a resistor network is employed to control the gain level. The DFE utilizes a half-rate unrolled structure and employs four floating taps to extend the clock range that can be equalized. The adaptive equalization is achieved through the Symbolized Least Mean Square (SS-LMS) algorithm based on pattern detection. The designed adaptive equalization algorithm consists of three components: Algorithm 1 for state calculation, Algorithm 2 for updating adaptive coefficient, Algorithm 3 for updating floating tap position. Through MATLAB simulations, it was validated that the 32 Gbps SerDes utilizing this adaptive equalization algorithm achieved an eye diagram opening margin of 0.81 Unit Interval (UI) and a bit error rate (BER) of 1.66e-17 under a channel insertion loss of 32 dB. This equalization algorithm can effectively reduce the error rate in data transmission, enhancing the reliability of the SerDes system.