Development of Recurrent Method of Logarithmic Analogue-to-Digital Conversion on Switched Capacitors with Charge Redistribution for Increased Speed

This article is devoted to the development of a recurrent method of logarithmic analogue–digital conversion on switched capacitors with charge redistribution, which differs from known methods by the fact that multiple returns will only affect the older bit. The essence of the method and its implementation are presented. Mathematical models of recurrent logarithmic ADCs (LADCs) based on this method have been developed, analysis has been carried out, and an assessment of errors and speed is given. It is shown that such recurrent LADCs have four or more times higher speed than known analogues. For example, 10-bit LADCs in the range of input voltages from 1 mV to 10 V provide 12-bit and 14-bit accuracy, the conversion time is less than 203 μs and 748 μs with the number of conversion tacts being 81 and 299, and the error of the output code is no more than 0.003% and 0.0007%, respectively.