Design an 20-Bit, 20 MS/s Pipeline ADC on 90nm CMOS with 154.57dB SFDR

This paper introduces innovative high-speed, high-resolution pipeline ADC architecture, designed with a 1.8V supply voltage and simulated using 90nm CMOS technology in Cadence. The proposed design achieves a 20-bit resolution with a sampling rate of 20 MS/s while maintaining an efficient power consumption of 16.7mW. Operating at a 1 kHz input frequency, this converter is particularly well-suited for biomedical monitoring systems. Performance metrics reveal impressive results: 154.57 dB spurious-free dynamic range (SFDR), 18.75 effective number of bits (ENOB), and differential non-linearity (DNL) values ranging from -0.18 LSB to +0.4 LSB. The design maintains exceptional power efficiency, consuming only 16.7mW at 1.8V supply voltage. These characteristics position our ADC as an excellent choice for both biomedical instruments and precision measurement systems requiring high-resolution signal conversion.