Design of A Sparse Convolutional Neural Network Accelerator

Large-scale convolutional neural networks have high computational complexity and large resource overhead, which greatly increases the hardware deployment cost of deep learning algorithms. In order to solve the problem of hardware implementation of convolutional neural network calculations, most of the previous designs of convolutional neural network accelerators focused on solving the bottlenecks of computing performance and bandwidth, ignoring the importance of convolutional neural network sparsity to accelerator design. In recent years, sparse convolutional neural network accelerator designs that can utilize sparsity often find it difficult to fully utilize parameter sparsity and activation sparsity at the same time, and there is a problem of load imbalance, resulting in low hardware computing efficiency. This paper proposes a sparse convolutional neural network accelerator architecture that can simultaneously utilize parameter sparsity and activation sparsity, and adopts a coarse-grained pruning method and the input cache designed in the sparse computing unit in the hardware to ensure the load balance of each sparse computing unit and improve computing efficiency. This paper implements the proposed accelerator hardware architecture on the XilinxAX7Z035ZYNQ target device. The research results show that when running the VGG-16 network, the effective throughput is 135.6GOPs, the power consumption is 5.306W, and the energy efficiency is 25.4GOPs/W. Compared with the existing convolutional neural network accelerator, the power consumption is reduced by 1.3∼4.4×, and the energy efficiency is improved by 1.1∼4.7×.