A 12b 125MSs Pipelined-SAR ADC For Medical Imaging Information Processing

This work presents a 12-bit 125MS/s pipelined-successive-approximation-register (pipelined-SAR) analog-to-digital converter (ADC) with a three-stage gain-boosted cascode floating inverter amplifier (GC-FIA) as the residue amplifier (RA). By adding auxiliary amplifiers to the third-stage structure in our GC-FIA, the open-loop gain can be greatly extended. Moreover, settling time and process, voltage and temperature (PVT) stability has been also improved in our work compared to original FIA structures. To confirm the effectiveness of proposed RA, entire pipelined-SAR ADC is designed and verified in 65nm CMOS process. Simulation results demonstrated that the signal-to-noise and distortion ratio (SNDR) and the spurious-free dynamic range (SFDR) are 73.2dB and 85.3dB at 125MS/s, respectively, while consumes only 3.5mW, leading to a 175.7dB Schreier FoM (FoMS) and 7.5fJ/conversion-step Walden FoM (FoMW). The proposed ADC is suitable for medical imaging information processing due to its good performance.