Research and Implementation of Extended Instruction Set for Smart Industrial Vision

With the rapid development of artificial intelligence technology, the demand for efficient image processing in automated inspection and quality control within intelligent industrial vision is increasing. However, existing general-purpose processors often struggle to meet the industrial-grade performance requirements for handling complex image-processing tasks. To address this challenge, this paper proposes a set of extended instruction sets based on the RISC-V architecture to accelerate computations for median filtering, gradient squared computation, threshold comparison, and image greyscaling. The consumption of decoding logic resources is reduced by using one-hot encoding for Funct7. A dedicated Image Processing Unit (IPU) is also designed to accelerate image processing computations further. The experiments were conducted on a Xilinx Artix-7 XC7A35T FPGA platform, and the results demonstrate that, compared to processors using the standard RISC-V integer instruction set, the processing cycles of the four designed extended instructions are reduced by 73% to 85%. Moreover, the overall image processing performance is improved by four times, significantly enhancing the system's execution efficiency.

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Publication Details

Published
2024-09-20
DOI
https://doi.org/10.1145/3703935.3704110
Primary Topic
Advanced Computing and Algorithms
Type
article
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article

Research and Implementation of Extended Instruction Set for Smart Industrial Vision

Qihu Xie, Yang Xiao-feng, Gang Cai, Zhihong Huang
Advanced Computing and Algorithms
article

Research and Implementation of Extended Instruction Set for Smart Industrial Vision

Qihu Xie, Yang Xiao-feng, Gang Cai, Zhihong Huang
article en

Abstract

With the rapid development of artificial intelligence technology, the demand for efficient image processing in automated inspection and quality control within intelligent industrial vision is increasing. However, existing general-purpose processors often struggle to meet the industrial-grade performance requirements for handling complex image-processing tasks. To address this challenge, this paper proposes a set of extended instruction sets based on the RISC-V architecture to accelerate computations for median filtering, gradient squared computation, threshold comparison, and image greyscaling. The consumption of decoding logic resources is reduced by using one-hot encoding for Funct7. A dedicated Image Processing Unit (IPU) is also designed to accelerate image processing computations further. The experiments were conducted on a Xilinx Artix-7 XC7A35T FPGA platform, and the results demonstrate that, compared to processors using the standard RISC-V integer instruction set, the processing cycles of the four designed extended instructions are reduced by 73% to 85%. Moreover, the overall image processing performance is improved by four times, significantly enhancing the system's execution efficiency.

Chinese Academy of Sciences (CN), Beijing Microelectronics Technology Institute (CN), Xi’an University of Posts and Telecommunications (CN), Aerospace Information Research Institute (CN)
Industry, innovation and infrastructure
Openalex Percentile: Top 48%
Advanced Computing and Algorithms
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