Enhanced model predictive current framework for a PMSM powered by three-level NPC inverters with DC-link voltage self-balancing mechanisms

This research presents an enhanced model predictive current control strategy for a three-level Neutral Point Clamped inverter driving a permanent magnet synchronous motor. The proposed new strategy significantly reduces computational complexity and balances the DC-bus capacitor voltages without weighting factors. Unlike conventional finite control set model predictive control, which requires exhaustive searches through all feasible switching conditions during iterative optimization, the proposed method streamlines a two-stage optimization procedure. In the initial stage, it utilizes the switching state of a P-type small vector. Medium voltage vectors are reconstructed from two suitable small vectors before the rolling optimization. Finally, the most effective switching signals are implemented in the 3L-NPC inverter by combining the best switching states identified in the optimization loop with the facilitated suggested self-balancing mechanisms for small vectors. The effectiveness of the suggested technique is validated via comprehensive comparative simulations and processor-in-loop experiments, executed under both stable and dynamic transitional conditions. The suggested approach achieves performance levels similar to traditional methods regarding settling time for speed, current ripple, and harmonic distortion of the current, all while decreasing the computational load by 30%. Compared to the prior method, capacitor voltage balancing is guaranteed under all operating conditions, particularly at low speeds. This result reduces stator current total harmonic distortion by 49.8% at 500 rpm due to the corrective of the medium voltage vector's impact. • Model predictive current control strategy for a three-level Neutral Point Clamped inverter driving a permanent magnet synchronous motor. • The suggested approach achieves performance levels similar to conventional FCS-MPC, while decreasing the computational load by 30%. • Compared to the prior method, capacitor voltage balancing is guaranteed under all operating conditions, particularly at low speeds.