Design of Power and Area Optimized 16 – bit Multiplier

In digital signal processing (DSP) applications, multiplication is a critical operation where the emphasis is often placed on speed and efficiency rather than absolute accuracy, given the millions of computations executed in each cycle. Multipliers influence energy consumption, critical path delay, and resource utilization the most. These impacts are particularly significant in FPGA (Field-Programmable Gate Array)-based designs. To address these challenges, this work proposes a modified radix 4 Booth multiplier with Dadda tree for partial product reduction and a carry look ahead adder along with Bewicks SE (sign extension) to account for sign extension error that is optimized for area, featuring low latency and energy efficiency. When compared to other models, this approach demonstrates reduction in area, and energy consumption by up to 42.2% and 76.4%, respectively.