FlexPE: Flexible Processing Elements for Workload Optimization and Acceleration on FPGAs

Modern applications in the fields of machine learning, and scientific computing benefit from custom hardware configurations. In these cases, rather than designing or remapping the algorithms onto new accelerators, we propose flexible Processing Elements (PEs) that can adapt or reconfigure themselves according to the data type and compute type of the workloads. In this paper, we propose FlexPE, a framework that can generate reconfigurable and flexible (shrinkable or expandable) PEs according to the workload. It can generate an Field Programmable Gate Array (FPGA)-based custom accelerator in Register Transfer Language (RTL) with exactly the type of computations/data types required for the workload so that idle resources are not instantiated. FlexPE is evaluated on AMD-Xilinx ZedBoard and ZCU-104 FPGAs on PolyBench and MachSuite workloads. Through this approach, we achieve a remarkable reduction of resources by nearly 35x on the FPGAs. We achieve an impressive throughput increase of 81x and 43x on the two FPGAs on average, and 35x reduction in resources compared to related work.