A Compact SHA256 Accelerator in 22nm for Energy Bounded Use-Cases with 8.2GHash/J

A 6.8•10<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup> μm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> SHA256 hardware accelerator, achieving 8.2GHash/J and 3MHash/s throughput at 460mV, is fabricated in 22nm CMOS. Round-based dataflow with added pipelining and hybrid shift-FIFO structure provides 31% increase in clock frequency and 21% reduction in energy consumption. Replacing DFFs with pulsed D-latch can further increase clock frequency by 15% and decrease energy cost by 13%. Combination of high energy efficiency, high clock frequency and compact area makes the proposed SHA256 engines suitable for a wide range of applications spanning from IoT to bitcoin mining.