Biased Compressor Based Approximate Multiplier Design Using Genetic Algorithm
Multiplication is the cornerstone in a vast array of applications. The employment of approximate multipliers offers a significant advantage in improving system performance. In this work, we conduct an in-depth and comprehensive analysis of various compressors, analyze their error distributions and propose a set of compressors with biased errors. By configuring heterogeneous compressors via a genetic algorithm and optimizing the input order of compressors, we propose several multipliers. Experimental results show that these multipliers have lower power, delay and area consumption compared with the state-of-the-art approximate multipliers. Notably, the AM_4 multiplier, without reducing the accuracy in image recognition and with an image blending PSNR exceeding 50, has reduced the area overhead by 27.3%, power consumption by 49.2%, and delay by 15.2% compared to the precise multiplier.
Authors
- Shangshang Yao (ORCID: https://orcid.org/0000-0001-7217-1712)
- Jianmin Zhang (ORCID: https://orcid.org/0000-0003-3271-246X)
- Weikang Xu (ORCID: https://orcid.org/0000-0002-4120-9455)
- Yan Sun (ORCID: https://orcid.org/0000-0002-9582-1578)
- Zhiqiang Wen (ORCID: https://orcid.org/0000-0002-0433-8856)
Institutions
- National University of Defense Technology (CN)
Publication Details
- Published
- 2025-05-25
- DOI
- https://doi.org/10.1109/iscas56072.2025.11043336
- Primary Topic
- Low-power high-performance VLSI design
- Type
- article
- Field-Weighted Citation Impact
- 0.00
Funders
- National Key Research and Development Program of China