Design and Application of a Novel Readout ASIC for SiPM Array

A low-power, 64-channel readout chip, named FESA(Front End for SiPM Array), is designed and tapped out in this paper, which uses a row and column summing readout method to reduce the number of output channels and converts the signal amplitude into time width output by linear discharge method. These output signals are then measured by FPGA-based TDCs so that the energy and time information of the event can be obtained simultaneously. The outstanding advantages of the chip are simplicity and low power consumption without compromise of measurement performance. Based on the chip, a novel and compact PET detector module with high-performance readout electronics was developed and validated. Six FESA chips, each connecting to one PET detector head based on 8×8 SiPM array, are packed onto a printed circuit board (PCB) sharing one FPGA for data processing and communication, which enables the detector modules can be easily arranged for constructing different type of PET systems. The FESA chip was evaluated with timing precision better than 20 ps, linearity of 99.55% and measurement dynamic range of 150 times. The designed detector module (SiPM coupling with LYSO crystal array) was also evaluated with 1 mm positioning precision, 18.3% energy resolution and 461 ps dual-module coincidence timing resolution. The test results show that the FESA chip and the module electronics can achieve acceptable performance in the industry, but at the same time have the characteristics of power saving, simplicity and high flexibility.