A High-Speed 8-bit Single-Channel SAR ADC with Tailored Bit Intervals

This paper presents a high-speed 8-bit asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) featuring tailored bit intervals (TBI). The design employs built-in SAR logic to set delays autonomously, eliminating the need for digital assistance, and thereby reducing both power and area consumption. This approach also effectively shortens the waiting time before lower-bit comparisons, enabling faster conversions. The ADC is simulated in the 16 nm process, occupying only 0.0012 mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>, with post-simulation conducted under various extreme process and temperature conditions. Compared to prior works, our design exhibits notable performance advantages, achieving an ENOB of 7.38 bits at TT 25°C with a power consumption of 6.94 mW. Furthermore, the designed TBI-ADC attains a sampling rate of 1.6 GS/s at FF -40°C, representing a 33% increase over the fastest previously reported single-channel, 1b/cycle, 8-bit SAR ADC.