An In-Memory Computing Architecture Utilizing A 1Capacitor-1Nanoelectromechanical Switch Device

This brief introduces an in-memory computing (IMC) architecture utilizing a novel analog pop-count circuit based on the one-capacitor-one-nanoelectromechanical (NEM) memory switch device (1C-1N) structure, which performs XNOR and pop-count operations for binary neural networks (BNNs). The NEM memory switch device is a non-volatile memory (NVM) device capable of performing logic-in-memory operations such as XNOR operation. The analog pop-count circuit functions as a readout circuit for the NEM memory switch, reusing the 1C-1N structure as a capacitor digital-to-analog converter. The proposed 1C-1N device and the analog pop-count circuit are simulated using 28-nm CMOS technology. The results show that the 1C-1N device consumes an extremely low read power of 1-fJ/bit and the overall scheme utilizing the analog pop-count circuit, achieves 448.8 TOPS/W while achieving 49.5-% less area than using an analog-to-digital converter (ADC).