A 4.5-Track Standard Cell Library with Buried Power Rails in 7nm Node

In this paper we present a 4.5-track standard cell library using ASAP7 PDK extended to support buried-power rails and backside metal wires for power distribution. This work showcases a successful implementation of a 4.5-track cell library by a co-optimization performed at process, cell, and chip levels. Experimental results show that the 4.5-track cell library can improve the ratio of timing performance to area and the ratio of timing performance to power dissipation by 43% and 27% respectively when compared with the results obtained with a six-track cell library.