Partitioning SFQ Circuits for Serial Biasing in Heterogeneous Circuits

The significant bias currents in large scale single flux quantum (SFQ) systems can greatly tax the power delivery system and lead to system failure. Current recycling is a technique that reduces bias currents in SFQ systems by dividing similar circuits into several blocks or partitions. Each block is placed on a different ground plane and serially biased. Since the circuit block is placed on a different ground, a driver-receiver pair (DRP) is used to transfer clock or data signals between the circuit blocks. Current recycling is extended here to different circuit blocks with varying bias current requirements, described as a heterogeneous circuit. Current recycling in heterogeneous circuits is feasible with current biasing techniques: dummy Josephson transmission lines (JTL) can be inserted into those systems with small bias imbalances, while resistive trees can be used in those systems with large bias imbalances. A partitioning algorithm for heterogeneous circuits is proposed to address the large bias imbalance that occurs after inserting DRPs. This partitioning algorithm uses a combination of the Kernighan–Lin (KL) and Fiduccia-Mattheyses (FM) algorithms while minimizing the number of DRPs. The heterogeneous partitioning algorithm is demonstrated on several ISCAS’89 benchmark circuits, incorporating both resistive tree and DRP insertion to achieve an average reduction of 29.7% in current, 31% reduction in DRPs, and a 40.9% reduction in the number of Josephson junctions.