Dynamic ADC and Equalizer Adaptation with Background SNR Monitoring for a DSP-Based PAM-4 Receiver

ADC-DSP-based PAM-4 receivers are widely used in 100+ Gbps data links to compensate for high channel losses through flexible digital equalization. To support applications ranging from very short- to long-reach, where channel loss can vary by over 20 dB, it is crucial to incorporate both channel-adaptive ADCs and equalizers for optimizing energy efficiency during operation. This paper introduces a system controller with an integrated SNR monitor that dynamically reconfigures the ADC resolution and FFE tap count in the background. By maintaining a relatively constant SNR at the input of the PAM-4 demodulator, hardware resources are co-optimized to reduce power consumption while achieving a target bit error rate (BER) of 10<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-6</sup>. A digital engine for a 112 Gb/s PAM-4 receiver, featuring a 1-tap DFE and reconfigurable ADC and FFE, is implemented to handle channel losses ranging from 12.4 dB to 34.5 dB. By automatically reducing the ADC resolution and FFE taps from 6 to 5 bits and from 24 to 6 taps, respectively, power savings of over 40% are achieved.