Towards Improving Memory Access in Large-Scale NoC-based Systems

Frequent and inconsistent main-memory requests in large-scale Network-on-Chip (NoC) systems pose significant performance challenges. While strategies like multi-level cache hierarchies and network resource optimization mitigate memory bottlenecks, their impact on the statistical predictability of memory access remains underexplored.We propose a structured methodology to guide the design of NoC-based systems by balancing the tradeoff between the statistical predictability of memory access and the average throughput of the memory controller (MC). Using Power Spectral Density (PSD) of inter-packet arrival times (IPAT) at MC, we evaluate the impact of key architectural parameters, cache size, buffer size, and network size on memory access predictability. We analyze changes in PSD characteristics, including stationarity, monofractal chaos, and multifractal chaos, alongside average MC throughput to identify optimal parameter values that maximize both predictability and throughput. Our results demonstrate that fine-tuning these parameters can alleviate chaoticity in IPAT at MC, thereby providing a valuable framework for designing efficient NoC-based systems across diverse applications.