A Highly PVT Invariant Low Power Scalable Analog Dynamic Current-Mode Translinear Matrix-Vector Multiplier

Many demanding applications of signal processing and neural networks require scalable, precise and energy efficient matrix-vector multipliers. Translinear MOS circuits, which use logarithmically compressed subthreshold voltages to control linear currents, could offer a particularly dense solution with high dynamic range. However, their susceptibility to Process, Voltage and Temperature (PVT) variations has thus far hindered their use in large arrays. Therefore, we propose a scalable translinear matrix-vector multiplier array, comprising only two transistors and one capacitor per cell, that offers very high PVT invariance. We employ two techniques to achieve this: first, we use dynamic current mirroring within the individual multiplier cells. Second, we store the matrix coefficients using a correlated double sampling (CDS) scheme that is highly invariant to process and voltage variations. To improve retention, stored weights are periodically refreshed through the same CDS scheme, which also compensates for 1/f noise and temperature variations. This refresh is fast and row parallel, allowing our proposed array to scale to millions of weights. We designed and verified the proposed architecture through transistor-level simulation in a 22 nm CMOS process. At less than 0.5 fJ per multiply-accumulate operation, this architecture is especially promising for scalable low-power applications.