APCer: An Agile Physical Compiler for Multi-Port Register File

This paper proposes a novel Agile Physical Compiler (APCer) for multi-port register files based on a standard cell library. It employs a Performance, Power and Area (PPA)-driven genetic algorithm to facilitate agile iterations and design generation. APCer can automatically iterate, generate, and optimize floorplan, rapidly creating efficient register file circuits and layouts with specified capacity and port numbers. Additionally, APCer responds to user-defined PPA requirements, enabling targeted design optimizations. It accelerates the register file design duration by over 40× and 20× compared with the full custom approach and existing compilers, respectively. Compared to existing compilers, APCer improves performance by 20.7% and reduces power consumption by 33.9%. Compared to the full custom approach, APCer improves performance by 31.5% and reduces power consumption by 28.8%.