LPRE: Logarithmic Posit-enabled Reconfigurable edge-AI Engine
Edge-AI applications face huge challenges in resource-constrained environments, particularly in enhancing computational efficiency within bandwidth limitations. This work proposes the Logarithmic-Posit-enabled Reconfigurable edgeAI Engine (LPRE) that enhances hardware efficiency without compromising accuracy. The proposed architecture utilizes time-multiplexed dynamically configurable single-layer hardware to balance resource reuse and bandwidth for multi-layer perceptron and CNN models. Evaluations on LeNet-5 using MNIST demonstrate that LPRE achieves up to 4× throughput enhancement at 8-bit precision with negligible accuracy loss (compared to FP32 baseline), while requiring up to 80% and 50% fewer resources than fixed-point arithmetic and state-of-the-art works, respectively. The design is viable for various edge-AI applications, such as real-time number plate recognition, offering scalable, energy-efficient IoT solutions.
Authors
- Adam Teman (ORCID: https://orcid.org/0000-0002-8233-4711)
- Gopal Raut (ORCID: https://orcid.org/0000-0002-1046-9457)
- Santosh Kumar Vishvakarma (ORCID: https://orcid.org/0000-0003-4223-0077)
- Omkar Kokane
- Mukul Lokhande (ORCID: https://orcid.org/0009-0001-8903-5159)
Institutions
- Centre for Development of Advanced Computing (IN)
- Bar-Ilan University (IL)
- Indian Institute of Technology Indore (IN)
Publication Details
- Published
- 2025-05-25
- DOI
- https://doi.org/10.1109/iscas56072.2025.11043622
- Citations
- 4
- Primary Topic
- Embedded Systems Design Techniques
- Type
- article
- Field-Weighted Citation Impact
- 9.08