GDS2SEM: Diffusion-based Layout-to-SEM Post-Fabrication Emulation for IC Validation

Continued technology scaling and ever shrinking feature sizes in Integrated Circuit (IC) layouts cause those layouts to look like highly idealized versions of the true structures on a manufactured IC. However, there are a number of instances where we need to be able to link the ideal and manufactured layouts like for quality control and reverse engineering. The imaging of ICs is performed via Scanning Electron Microscopy (SEM). It is a complex and expensive process which is invaluable when debugging technology problems or finding circuit defects. An alternative is SEM or Lithography Simulation, where physics-based models of the imaging process can be used to predict the manufactured layout, which is also is highly complex and resource consuming process. Data-driven simulators also suffer from the limited amount of publicly available IC design data for training. In this paper, we present GDS2SEM, a data-driven and diffusion-based alternative to understanding the relationship between ideal and manufactured layouts, which can help us generate new Layout-SEM image data. We formulate the Layout-to-SEM mapping as a machine learning image-to-image translation task. We show that it is possible to create such an accurate mapping, and demonstrate it on a number of layouts. We also showcase the potential that this method holds for data augmentation by testing its generative capabilities on unseen data.