A ±0.6 dB, 256-μW Digital-Intensive RSSI with 80-dB Dynamic-Range in 65-nm CMOS

Received signal strength indicator (RSSI) is indispensable in modern wireless communications for detecting and measuring signal strength. This paper presents a new RSSI system architecture that addresses the constraints of conventional designs. Traditional RSSI systems implemented at the RF level encounter challenges such as limited dynamic range and impedance matching, while baseband implementations contend with high power consumption and depend on analog-to-digital converters (ADCs) to digitize signal strength. Moreover, the large dynamic range necessitates high-resolution ADCs, which further exacerbates area and power consumption. The proposed RSSI architecture at baseband mitigates these challenges by employing a limiting amplifier, followed by a peak detector and comparator at each stage, thus eliminating the need for an ADC. This configuration enables coarse control and provides the most significant bits (MSBs) of the RSSI. Additionally, a programmable gain amplifier in conjunction with an up-counter captures the least significant bits (LSBs) of the RSSI, providing fine control. The system is implemented in a 65 nm CMOS process, operating at 1.2 V, with a power consumption of 256 μW. It achieves a wide dynamic range of 80-dB and a detection accuracy of ±0.6 dB, as validated through detailed simulations.