Benchmarking Cryogenic Circuits using 5 nm FinFETs for Quantum Processing

Quantum computing offers the potential to solve problems that are intractable for classical computers. A major challenge in scaling quantum computers lies in bridging the gap between cryogenic qubits, operating at millikelvin to few kelvin temperatures, and the classical CMOS-based system-on-chip (SoC) typically located at room temperature (300K). This connection introduces heat leakage, which can destabilize the qubit states. A promising solution is to relocate the control circuits and processors to the cryogenic environment, but this imposes strict constraints on power consumption due to limited cooling capacity. Additionally, the SoC must meet stringent timing requirements for qubit measurement classification. In this work, we investigate the performance of CMOS-based circuits for cryogenic operations using 5 nm FinFET technology. We begin by measuring the electrical characteristics of advanced 5 nm FinFETs at both 10K and 300K. Using these measured data, we calibrate the industry-standard compact model (BSIM-CMG) and develop two standard cell libraries for each temperature. Through the logic synthesis of six circuits from the EPFL benchmark suite, we analyze their behavior at cryogenic temperatures. Our results show that circuits at 10K achieve a 41% increase in speed compared to 300K. Further, they operate efficiently at lower supply voltages, which enables reduced power consumption while maintaining high-speed performance in cryogenic environments.