A Memory-Based Continuous-Flow FFT Processor with a Conflict-Free In-Place Addressing Scheme Supporting Composite Power Points

A configurable fast Fourier transform (FFT) processor capable of computing composite power points becomes prevailing in recent communication and signal processing systems. In this paper, a continuous-flow memory-based FFT processor is designed to support 63 modes from 32 to 4096 points. A conflict-free and in-place addressing scheme is proposed to minimize the number of memory banks and total memory sizes for input buffering, intermediate storage, and output re-ordering. The processing element handles radix-3, radix-4, radix-5, radix-(4•2), radix- 3<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>, radix-4<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> butterflies using a multi-path delay commutator (MDC) architecture with up to five parallel paths. Besides, the 3-tuple multi-radix representation is adopted for the virtual address generation and thus we can extend the concept of conventional conflict-free and in-place addressing for physical address and bank assignments beyond power-of-2 cases. From the comparison results, our proposed FFT processor architecture demonstrates strong computational efficiency by considering both the arithmetic complexity of butterfly operations and twiddle-factor multipliers as well as throughput.