Analysis of Dynamic Errors in Tri-level DACs for Continuous-Time Delta-Sigma Modulators

Tri-level current-steering digital-to-analog converters (DACs) offer an appealing balance between resolution and static linearity, making them attractive to be employed as feedback DAC in high-resolution continuous-time Delta-Sigma-Modulator (CTDSM). However, they are susceptible to non-linearity caused by dynamic, signal-dependent switching errors degrading the overall performance. While such errors have been thoroughly analyzed in literature for single-bit current-steering DACs, they have not been thoroughly investigated for tri-level current-steering DACs. As a result, this paper investigates the sources of these errors and demonstrates their severity by analysis and simulations employing a tri-level DAC in an exemplary CTDSM. In addition, techniques for mitigating dynamic errors, including device sizing and switching schemes, are discussed to help mitigate the non-linearity.