A Calibration Free 8-to-12 b, 1-to-20 MSPS Reconfigurable SAR ADC with Optimized Window-Switching Scheme

This paper presents a novel 8-to-12 b, 1-to-20 MSPS Reconfigurable SAR ADC for low power multi-standard systems to avoid multi-ADCs’ integration in SoC designs thus reducing power and area. To enhance power efficiency across varying conversion rates and resolutions, proposed ADC integrates a custom-designed source-degeneration dynamic comparator along with a reconfigurable asynchronous mechanism. Furthermore, to broaden its applicability, the ADC utilizes an optimized window-switching (OWS) scheme to mitigate dynamic and static performance degradation stemming from capacitor array nonlinearity without the need for additional calibration algorithms. The prototype is designed in 40nm CMOS process with 1.2 V supply and occupied an active area of 0.0445mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>. Post-simulation results show that ADC’s 8b 1MSPS mode achieves SNDR of 48.86 dB, SFDR of 64.49 dB and FoM<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">W</inf> of 154.5 fJ/conv-step. And 10b 5MSPS achieves SNDR of 60.89 dB, SFDR of 74.23 dB and FoM<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">W</inf> of 45.8 fJ/conv-step. 12b 20MSPS achieves SNDR of 70.33 dB, SFDR of 83.59 dB and FoM<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">W</inf> of 16.4 fJ/conv-step.