Low-Overhead Calibration Scheme for Segmented High-Resolution Current-Steering DACs

A calibration scheme for Segmented High-Resolution Current-Steering DACs is presented that enhances DAC SFDR without degrading DAC SNR as is the case with randomization-based Dynamic Element Matching (DEM) techniques and especially due to repetitive element switching transients when DEM is operational. A Segmented 13-bit 200MS/s DAC is designed to validate the proposed calibration scheme. With 2% σ DAC element mismatch, post-calibration transistor-level SNR of 73.4dB and SFDR of 80dB was achieved. The proposed scheme demonstrates 4.6dB SNR and 8dB SFDR improvement over DEM for mismatch alone. The DAC has 1.2Vpp Single-Ended Output Range and with 3.6nV/rt-Hz 1MHz Output Noise, meets Low-Phase-Noise requirements for Two-Point-Modulated Frequency-Modulated Continuous-Wave Radar Phase Locked Loop applications. It was implemented using 1.8V devices in Global-Foundries 1P10M 22nm FD-SOI CMOS technology, occupies 0.13mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> area and consumes 19mA current from 1.6V supply.